India Semiconductor
Investment Playbook
India will need $300B in semiconductors by 2035. It imports almost all of them today. This is the investment playbook for the decade-long supply gap - where to build, what to build, and how we evaluate the founders doing it.

Kaustubh Savant
Author

Natasha Kumar
Contributor

Krittik Vemuri
Contributor

Ramakanth Alapati
Expert Review
Setup
Foreword: Why This, Why Now
The global semiconductor industry crossed $796 billion in 2025 - its biggest year ever - and is tracking toward $975 billion by 2026. Almost half of that growth is driven by AI accelerators and the infrastructure built to run them. The chip has stopped being a component and become the strategic resource of the 21st century; every major economy has now understood this and is acting accordingly.
India has understood it too, but from a distinctive position. It will consume an estimated $120 billion of semiconductors by 2030 and $300 billion by 2035. It currently designs almost none and fabricates less than 1% of what it uses. That gap - between demand and domestic supply - is the investment thesis this playbook defends.
The government has responded at scale. The India Semiconductor Mission, the Production Linked Incentive scheme, and the $10 billion Semiconductor and Display Fab Ecosystem programme have collectively committed over $19 billion in fiscal support - more than all private venture capital that has ever flowed into the sector. Three fab projects are now under construction. But government capital cannot build a complete ecosystem. What fills the gaps between the fabs is the opportunity this report maps.
This is not a market overview. It is a working document - our thinking on where venture capital can play in India's semiconductor build-out, which founders are positioned to win, and how we evaluate them. We publish it because we believe the analysis is useful, and because the best founders should know how we think before they walk in the door.
Setup
Who This Is For
Two readers. Founders building in the semiconductor value chain - design houses, EDA tools, specialty materials, packaging, chip-enabled systems - who want to understand where the durable demand is, what the policy environment makes possible, and how an investor reads their opportunity. And investors - LPs, co-investors, and family offices - underwriting the India deep-tech thesis, who need to know where semiconductors fit in the larger sovereign-technology picture.
Scope note
We treat as in-scope any company whose core technology sits in the semiconductor value chain - from chip design and EDA through fabrication, advanced packaging, and test, to materials, equipment, and the chip-enabled systems that create the pull. We do not cover commodity consumer electronics assembly; we do cover the high-value subsystems that define what those products are capable of.
Setup
What You'll Walk Away Knowing
Claim 01
The global chip cycle has structurally decoupled from consumer electronics. AI infrastructure is now the primary demand driver, and it is not cyclical.
Claim 02
India's $300B import bill by 2035 is the single largest addressable supply gap in the semiconductor industry. No other market of comparable size is this underbuilt.
Claim 03
Government capital has de-risked the fab layer. The venture opportunity sits in design, packaging, materials, and the systems that create demand pull - not in fab replication.
Claim 04
India's right to win in semiconductors is not in leading-edge logic. It is in specialty analog, mixed-signal, power, and the application-specific design ecosystem that its engineering talent base can build.
Part I
The Global Chip Cycle and Why It Matters to India
The semiconductor market has been through five major cycles since 1990. What is happening now is structurally different. Understanding why matters to anyone building in India, because the shape of the global cycle determines which parts of the value chain can support new entrants.
The Cycle Has a New Engine: AI
Global chip revenues reached $527 billion in 2023, recovered to $645 billion in 2024, and accelerated to $796 billion in 2025 - the largest single-year dollar gain the industry has ever recorded. The primary driver was not consumer electronics recovering from the 2022 inventory correction. It was AI infrastructure: the accelerators, high-bandwidth memory, and advanced networking chips needed to build and run large models. The AI semiconductor segment grew from roughly 9% of the market in 2023 to 28% in 2025 and is tracking toward 34% by 2026.
Figure 1 - Global Semiconductor Revenue, 2023–2026E (US$B)
- Non-AI Chips
- AI Chips
Sources: SIA, WSTS, IDC, SilverX analysis. AI chip revenues include GPUs, AI ASICs, HBM.
What distinguishes this cycle from every prior one is the demand floor. Consumer electronics cycles reverse when inventory clears. AI infrastructure demand does not reverse - it compounds. Every model generation requires more compute, more memory bandwidth, and faster interconnects. The hyperscalers have made multi-year capital commitments that are structurally sticky: Microsoft, Google, Meta and Amazon together announced over $300 billion in 2025 capex, the majority directed at AI infrastructure. That is not a 12-month demand spike. It is a decade-long build.
The secondary effect - the one that matters most for India - is geopolitical. AI capability is now a national security priority for every major power. The US has restricted advanced chip exports to China; China has responded by accelerating domestic development at extraordinary cost. Europe, Japan, South Korea, and India have all launched national semiconductor programmes. Supply chains that ran through a handful of chokepoints are being deliberately diversified. That diversification is the structural opening.
$796B
Global chip revenue, 2025
Record year
$975B
Projected 2026E
+22% YoY
~28%
AI chip share of market, 2025
vs 9% in 2023
$300B+
Hyperscaler AI capex, 2025
Multi-year commitments
The Supply Chain Is Being Redrawn
The existing semiconductor supply chain is extraordinarily concentrated. TSMC produces approximately 92% of the world's most advanced logic chips, with ASML providing the EUV machines needed to make them - machines that itself sources over 5,000 components from a single-point-of-failure supply chain spread across three countries. The US CHIPS Act ($52 billion), Europe's Chips Act (€43 billion), Japan's semiconductor strategy ($7 billion), and India's ISM ($10 billion) are all expressions of the same recognised vulnerability.
The result is the first genuinely multi-polar semiconductor landscape in twenty years. New fabs are under construction in Arizona, Dresden, Kumamoto, and now Dholera and Sanand. None of them, in the near term, matches TSMC's process capability at the leading edge. All of them create opportunities in the supporting ecosystem - materials, chemicals, gases, equipment maintenance, design services, packaging, and test - that did not exist at scale outside Taiwan and South Korea five years ago.
Part II
Three Models for Winning in Semiconductors
Every country building semiconductor capacity is implicitly choosing a strategic model. The choice shapes everything - which parts of the value chain get capital, which get talent, and where the long-term margin lives. There are three distinct models in operation today.
Figure 2 - Three Value-Chain Models
🇹🇼 🇰🇷
The incumbent model
Global Efficiency
Optimise for cost and yield at scale. Run the fab at maximum utilisation. Win on process node leadership.
Defensible but capex-unlimited. New entrants cannot replicate on a decade timeline.
🇺🇸 🇪🇺 🇯🇵
The government-funded model
Sovereign Resilience
Use subsidies to onshore strategically important nodes, even at above-market cost. Accept margin compression for supply security.
Capital-intensive, government-directed. Creates ecosystem pull but not a venture-scale entry point in fab itself.
🇮🇳 ✦
The emerging model - India's opening
AI-Native Stack
Start from demand. Build the design and packaging layers that AI infrastructure requires. Let government fund the fab; let venture fund the rest.
Capital-efficient, talent-led, demand-pulled. The venture-fundable path.
India does not need to out-fab Taiwan. It needs to out-design, out-package, and out-integrate the applications that the next wave of AI infrastructure requires.
The AI-Native Stack model is not a consolation prize. Advanced packaging - chiplet integration, 2.5D and 3D stacking, heterogeneous integration - is where the semiconductor industry is moving because the physics of monolithic scaling is running out. The highest-value parts of the next generation of AI chips will not be in the logic die. They will be in how the dies are assembled, interconnected, and cooled. India's opportunity in advanced ATMP is not a fallback from leading-edge fab. It is a bet on where the value is going.
Part III
India's Demand Story
Every investment thesis requires a demand forecast. India's is unusually legible: the number is large, the drivers are structural, and the domestic supply is almost zero. The question is not whether demand exists. The question is which pockets of demand are reachable, on what timeline, and by what kind of company.
Figure 3 - India Semiconductor Demand Trajectory (US$B)
Sources: India Electronics and Semiconductor Association (IESA), ISM, SilverX analysis.
The Demand Engines
India's semiconductor demand is not monolithic. It is the sum of five distinct engines growing at very different rates. The headline number - $47.5B today to $300B by 2035 - masks a set of sectoral stories that determine which parts of the value chain get pulled first.
Figure 4 - Demand Engine CAGR to 2030 (%)
SilverX analysis; IESA sector forecasts.
Data Centres
~42% CAGRThe fastest-growing engine by far. India's hyperscaler build-out - driven by global AI investment, rising domestic cloud consumption, and a government Digital India Cloud infrastructure push - requires compute, networking, storage, and power management chips at scale. Demand here pulls directly on AI accelerators, high-speed networking ASICs, and power semiconductors. A $50B+ market by 2030, almost entirely imported today.
Defence & Aerospace
~28% CAGRForced indigenisation via the Positive Indigenisation Lists has placed radar processors, communication ICs, inertial measurement units, and power management chips for platforms on a mandatory domestic sourcing timeline. Post-Operation Sindoor, drone and counter-drone electronics are a procurement priority. Defence semiconductor demand is sticky, long-contract, and actively asking for domestic supply - one of the few sectors where the customer comes to the founder.
EVs & Automotive
~24% CAGRIndia is the world's second-largest two-wheeler market and a fast-growing four-wheeler market, with EV penetration accelerating. Each EV requires 2-3x the semiconductor content of an ICE vehicle: motor controllers, battery management systems, ADAS processors, power electronics. The pull is on SiC and GaN power semiconductors, microcontrollers, and automotive-grade analog - categories where India has design capability but almost no domestic supply.
Telecom & 5G
~18% CAGRIndia's 5G rollout requires baseband processors, RF front-ends, and network infrastructure chips. The government's telecom equipment PLI creates demand for domestically designed chips in base stations and core network equipment. A secondary pull comes from the satellite broadband build-out - Starlink, OneWeb, and Indian LEO players all create demand for phased-array antenna chips and ground-terminal semiconductors.
Consumer Electronics
~8% CAGRThe largest existing market by volume but the slowest-growing by semiconductor value. Smartphones, wearables, and appliances are assembled in India increasingly, but the chips inside are almost uniformly imported from Taiwan, South Korea, and China. The opportunity here is not in smartphone SoCs - that window has closed for new entrants - but in the power management, display driver, and audio processing chips where specialty design houses can compete.
The import gap is the investment case
India imported $30.3 billion of semiconductors in FY2025-26, up 23.3% year on year. It is on track to import over $50 billion annually by 2028. Every dollar of that import bill is a dollar of addressable revenue for a domestically designed and/or manufactured chip. The investment case does not depend on predicting which specific application wins. It depends only on the gap closing - slowly, partially, over a decade. Even 10% domestic supply share by 2030 is a $12 billion annual revenue pool that does not exist today.
Part IV
The Value Chain: Four Tiers, One Smile
The semiconductor value chain has four tiers. Each requires different capital, talent, and time horizons. Understanding the margin distribution across them - the "smile curve" - is the first step in locating where a venture-backed Indian company can actually compete.
Figure 5 - The Semiconductor Value Ecosystem (Four Tiers)
Tier 1
Design & IP
Chip architecture, IP blocks, EDA tools, verification, design services
ARM, Synopsys, Cadence, Qualcomm (fabless); India: Saankhya Labs, Mindgrove
Strong talent base. Venture-fundable. India's primary entry point.
Tier 2
Fabrication (Fab)
Wafer fabrication at various process nodes (28nm to 2nm leading edge)
TSMC, Samsung Foundry, Intel Foundry; India: Tata/PSMC (Dholera), CG Power/Renesas (Sanand)
Government-funded. Not the venture entry point except in specialty/legacy nodes.
Tier 3
ATMP / Packaging
Assembly, test, mark, pack; advanced packaging (chiplets, 2.5D/3D, substrate)
ASE, Amkor, OSAT leaders; India: Kaynes, Tata ATMP
Critical gap. Advanced packaging is the highest-growth sub-segment. Venture-relevant.
Tier 4
Systems & Enablers
Materials, chemicals, gases, equipment, PCB, system integration, test equipment
ASML, Applied Materials, Merck; India: Astra Microwave, SCI Semiconductors
Specialty materials and test are venture-fundable. Equipment is long-horizon.
Figure 6 - The Semiconductor Smile Curve: Profit Margin vs Capital Intensity
IP & EDA
Fabless Design
Foundry (Fab)
ATMP / OSAT
Systems / OEM
Indicative ranges based on public filings (TSMC, Qualcomm, ASML, ASE Group) and SilverX analysis.
The smile curve has a clear implication: the highest-returning segments are at the two ends - IP and design on the left, branded systems on the right. Fabrication sits in the trough: the most capital-intensive segment with the least flexible cost structure. India's government investment goes into the trough because it has to - fab is a strategic necessity. Venture capital should go to the ends, where talent drives more value than capital.
Part V
India's Right to Win
Identifying a market gap is necessary but not sufficient. The question that follows is: what gives India specifically the right to fill it? "Right to win" has two axes - the value India can actually offer in a given segment, and the structural advantage India holds that makes competing there durable rather than temporary.
Figure 7 - India's Right-to-Win: Value on Offer vs Structural Advantage
Pursue selectively
High value / Low structural advantage
- -LED / display drivers
- -IoT microcontrollers
- -MEMS sensors
Requires sustained policy support to compete
Primary focus
High value / High structural advantage
- -Application-specific AI chips (defence, EV, 5G)
- -Analog & mixed-signal design
- -Advanced ATMP / chiplet integration
- -Power semiconductors (SiC, GaN)
Venture-fundable, talent-led, demand-guaranteed
Avoid
Low value / Low structural advantage
- -Commodity DRAM / NAND
- -Legacy logic (trailing-edge fab only)
- -Standard commodity OSAT
No differentiation path for India
Build the moat
Low value now / High structural advantage
- -Specialty materials (SiC substrates, III-V compounds)
- -Process chemicals for Indian fabs
- -EDA tools for Indian design houses
Patient capital; 5–8 year horizon
SilverX framework. Structural advantage = combination of engineering talent depth, government demand signals, policy protection, and supply-chain co-location.
India's structural advantages in semiconductors are real and non-trivial. It graduates more engineers annually than any country except China, with a particularly deep base in VLSI design, embedded systems, and analog circuit design - the skills that application-specific chip design requires. Over 20% of the world's semiconductor design engineers work for companies headquartered in India or operating significant India design centres (Qualcomm, Intel, Texas Instruments, NXP, Infineon all have large Bangalore and Hyderabad presences).
What has changed in the last three years is policy structure. The ISM, PLI for semiconductors, and the ATMP-specific incentive scheme have created a funded demand environment that did not exist before 2022. Combined with defence indigenisation mandates that require domestic chips in specific systems, and a growing set of government buyers for 5G network equipment designed and made in India, the structural advantage is no longer just talent. It is talent plus guaranteed demand plus incentive-funded supply capacity.
Part VI
The Founder's Map: Seven Entry Points
The right-to-win analysis points to a primary quadrant. Within it, there are seven specific entry points that a venture-backed Indian company can realistically pursue today. They are organised under three strategic logics: Design-led, Packaging-led, and Enablers.
Figure 8 - The Founder's Map: Seven Entry Points under Three Strategic Logics
Design-Led
Custom chips for defence, EV powertrains, 5G base stations, and AI edge inference. The demand is mandated (defence PILs), incentivised (PLI electronics), and growing at 20-40% annually. Capital requirement: $5-25M for first silicon. India talent base: deep.
Power management, ADC/DAC, RF front-ends, motor controllers. Evergreen demand across every end-market; slower design cycles than digital; harder to offshore. India has more analog design talent per capita than almost any country outside the US.
The software layer that makes chip design possible. Synopsys and Cadence dominate, but AI-assisted design (LLM-guided layout, automated verification) is opening a wedge. India's software talent + semiconductor design knowledge = a rare combination that can compete here.
Packaging-Led
2.5D/3D chip stacking, fan-out wafer-level packaging, heterogeneous integration - the fastest-growing segment of the entire semiconductor value chain. Tata's ATMP facility is a start; the ecosystem around it (substrate, interposer, underfill, test) is almost entirely unbuilt in India.
The substrate is what the die sits on and connects through. Advanced packaging requires organic substrates, glass substrates, or silicon interposers - none of which India produces at scale. A bet on substrate supply is a bet on every chiplet-architecture chip that gets assembled in India.
Enablers
Silicon carbide (SiC) for EV power, gallium nitride (GaN) for RF and defence, III-V compounds for photonics and defence radar. These are the materials that define what the next generation of chips can do - and India has the raw mineral base (especially for SiC precursors) that no other major market can match.
Every chip must be tested. India's fab build-out creates immediate demand for wafer probe, final test, and reliability characterisation equipment and services. A domestically built semiconductor test ecosystem is a necessary infrastructure layer - and one that global test companies are only beginning to build in India.
SilverX investment framework, July 2026. Entry points are not mutually exclusive; several of the most compelling companies operate across two.
The most fundable companies in India's semiconductor ecosystem will be design-led, use government-funded fabs as their foundry, and capture margin at the ends of the smile curve the government cannot reach.
Part VII
The Capital Picture
India's semiconductor capital map is inverted relative to every other major tech sector. Government leads; private capital follows. Understanding why - and what it means for the venture entry point - is the critical context for any investment decision in this space.
Figure 9 - India's Semiconductor Capital Stack (Cumulative Commitments, US$B)
Government: ISM + PLI + SIS cumulative commitments. VC: all private venture and PE into India semiconductor companies, cumulative through 2025. SilverX analysis.
$10B+
India Semiconductor Mission committed
Fab + ATMP + display
$8B+
PLI electronics (chip-adjacent)
$11.2B
Cumulative private VC into India semis
All-time through 2025
<$1B
Early-stage VC (pre-Series B)
The gap we see
The implication is clear: the Indian government has committed to de-risking the capital-intensive layer. It has built the fabs, or is building them, with $10 billion in public money. It has subsidised the ATMP layer. What it has not and cannot do is build the design ecosystem, the materials supply chain, or the specialised test infrastructure. Those require talent-led, capital-efficient companies - exactly what venture capital is designed to fund.
The private capital market for India semiconductors is surprisingly thin for a sector of this strategic importance. Most of the $11.2 billion in cumulative private investment has gone into chip-enabled systems companies (smartphones, EVs, electronics manufacturing) rather than into the core semiconductor value chain itself. Pure-play chip design, advanced packaging, and materials companies have received a fraction of that total. The early-stage funding gap - Seed through Series B into core semiconductor companies - is the most undercapitalised segment of the Indian deep-tech ecosystem.
Why the funding gap exists and why it matters
Most generalist VCs lack the technical depth to evaluate chip design companies. The development cycles are long (18-36 months from concept to first silicon). Revenue is back-weighted. These features make semiconductor companies unattractive to funds optimised for 3-year deployment cycles and software-grade growth curves. The result is that the most technically capable Indian semiconductor founders - people who have spent careers at Qualcomm, Intel, or Texas Instruments and are now building their own companies - are systematically underfunded relative to their counterparts in the US or Taiwan. That is the market inefficiency SilverX exists to correct.
Part VIII
The Five-Lens Investment Framework
This is how SilverX evaluates semiconductor investment opportunities. Five lenses, each with a positive signal and a disqualifying red flag. A company must pass all five to proceed to term sheet; a single red flag in any lens is sufficient to decline, regardless of performance on the others.
Figure 10 - The Five-Lens Framework
| Lens | What We Look For | Red Flags |
|---|---|---|
| 1. Demand Anchor | A named, reachable customer that has an active problem the chip solves - ideally a government procurement programme (iDEX, PIL, PLI) or a large OEM with a confirmed design win. The customer does not need to be signed, but it must be real and not hypothetical. | No named customer beyond "the defence ministry will want this". Demand modelled entirely from TAM top-down with no bottom-up customer evidence. Reliance on a single export customer with no domestic fallback. |
| 2. Design Defensibility | A technical moat in the chip's architecture - a proprietary IP block, a novel algorithm implemented in silicon, a process optimisation that competitors cannot easily replicate. For analog and mixed-signal: demonstrated performance specs that exceed alternatives at comparable cost. For packaging: a process recipe not available from standard OSAT providers. | A chip that is functionally equivalent to an off-the-shelf component with no performance advantage. A design team that is replicating existing published architectures without modification. An "IP" claim that is actually a licensed third-party IP block with thin value-add. |
| 3. Foundry Access | A confirmed or confirmable foundry relationship that matches the technology node to the application. For most Indian chip startups this means a relationship with TSMC, UMC, Global Foundries, or Samsung Foundry at 28nm or above; or Tata's fab for commodity-node designs once operational. We look for evidence the founder understands tape-out economics and has a path to first silicon at reasonable dilution. | A business plan that requires leading-edge (3nm or 5nm) fab access with no existing relationship or contract. A team that has never taped out a chip. A capital plan that does not account for the $1-5M cost of first silicon and the 12-18 month development cycle. |
| 4. Team Depth | At minimum one founder with direct chip design experience - tapeout, characterisation, bring-up. For systems companies, at minimum one founder with deep embedded software experience at the silicon interface. For materials, at minimum one founder with materials science or process engineering credentials and lab access. Advisory boards do not substitute for technical founders. | A founder team with strong software credentials but no hardware or semiconductor experience, building a chip "because the market exists". An advisory board of retired chip executives substituting for a technical founding team. A team whose semiconductor design experience is limited to FPGA implementation. |
| 5. Capital Efficiency Path | A realistic plan from Seed investment to first silicon to first revenue in under 36 months, with a total capital requirement to revenue of under $15M for design companies and under $50M for materials/packaging. We are not looking for software-speed growth; we are looking for a defensible path to first customer that does not require a semiconductor fund-sized check to prove. | A capital plan that requires $100M+ to reach first revenue. A timeline to first silicon greater than 36 months. A revenue model that depends on licensing the IP rather than selling chips - unless the founder has prior IP licensing experience and a named potential licensee. |
The framework is designed to be fast. Most semiconductor pitches fail one of the five lenses within the first 30 minutes of a conversation. The value of having a framework is not to slow the evaluation down - it is to make the reason for a decline specific and useful to the founder, so they can fix the problem and return.
Close
Conclusion and Implications
The through-line is supply sovereignty and the economic opportunity it creates. India faces the largest addressable semiconductor supply gap of any country in the world - $300 billion in demand by 2035, almost none of it met by domestic production today. The government has responded with more capital than any other sector has attracted from public sources: over $19 billion committed to the fab and ATMP layer, with an explicit policy mandate to build a complete domestic ecosystem.
That government response creates the venture opportunity rather than crowding it out. By funding the capital-intensive foundation layer, the government has removed the largest barrier to entry for design-led and packaging-led companies. A chip startup in India in 2026 can access TSMC for leading-edge nodes, Tata's fab for mature nodes, and government-backed ATMP for packaging - none of which require the startup to invest in fabrication infrastructure. The design-to-market path has never been more capital-efficient.
What remains is the human layer: founders who understand chip design deeply enough to create defensible IP, who understand the procurement landscape well enough to navigate the customer journey, and who can build the applications that pull semiconductor demand forward. Finding and backing that cohort - early, before the market gets crowded - is what this playbook is about.
For Founders
Build where the demand is mandated and the import alternative is being foreclosed. Use the government's fab investments as your foundry; do not replicate them. Design for a named application and a named customer from day one. The worst semiconductor startups are the ones that design a chip looking for a use case. The best are the ones that start with an unsolvable application problem and work backward to silicon.
For Investors
The funding gap at early stage in India semiconductors is a structural opportunity, not a coincidence. The technical barrier to evaluation is real - but it is a moat for investors willing to build it, not a reason to avoid the sector. The right holding period is 7-10 years. The right return expectation is an industry that will produce $300 billion in annual demand by 2035, of which domestically built supply will capture a growing share. Position before that share becomes visible; it will not be cheap afterward.
| Term | Definition |
|---|---|
| ASIC | Application-Specific Integrated Circuit. A chip designed for a single specific function rather than general-purpose use. |
| ATMP | Assembly, Test, Mark, and Pack. The back-end of semiconductor manufacturing after the wafer leaves the fab. |
| Chiplet | A small, modular die designed to be combined with other chiplets in an advanced package to form a complete system. |
| EDA | Electronic Design Automation. Software tools used to design electronic systems, especially integrated circuits. |
| Fabless | A chip company that designs chips but does not own or operate its own fabrication facilities. Uses contract foundries (e.g. TSMC). |
| Foundry | A semiconductor fabrication plant that manufactures chips for other companies (fabless chip designers). |
| GaN | Gallium Nitride. A wide-bandgap semiconductor used in high-frequency, high-power applications including 5G RF and defence radar. |
| HBM | High Bandwidth Memory. A type of memory used in AI accelerators requiring very high data throughput. |
| IP Block | Intellectual Property block. A reusable unit of chip design logic (e.g. a CPU core, USB controller) licensed to chip designers. |
| ISM | India Semiconductor Mission. The government body overseeing India's semiconductor policy and incentive programmes. |
| Mixed-Signal | Chips that handle both analog and digital signals - common in sensors, power management, and RF systems. |
| OSAT | Outsourced Semiconductor Assembly and Test. Companies specialising in chip packaging and testing. |
| PLI | Production Linked Incentive. India's subsidy scheme providing financial incentives for domestic manufacturing. |
| PIL | Positive Indigenisation List. India's defence procurement mechanism that bans import of listed items, requiring domestic supply. |
| SiC | Silicon Carbide. A wide-bandgap semiconductor used in high-power, high-temperature applications, especially EV powertrains. |
| Tape-out | The final step in chip design when the design files are sent to the foundry to manufacture the first physical chips. |
| VLSI | Very Large Scale Integration. The process of creating an integrated circuit by combining thousands to billions of transistors. |
| Wafer | A thin slice of semiconductor material (usually silicon) on which integrated circuits are fabricated. |
